Semiconductor Industry Weekly #1: TSMC Capacity Crunch, H200 Policy Chaos, and the ASIC Duopoly
Semiconductor Industry Weekly
2026/05/21 17:04:25@Shenglan Huang

Semiconductor Industry Weekly #1: TSMC Capacity Crunch, H200 Policy Chaos, and the ASIC Duopoly

TSMC's 2nm and 3nm lines are fully booked through 2027, the H200 export framework is structurally contradictory, Intel EMIB gains hyperscaler design wins as CoWoS overflows, and Broadcom plus Marvell now control 80%+ of custom AI chip design.

Semiconductor Industry Weekly — Issue #1

Week of May 19–25, 2026 · Advanced nodes · Export controls · Foundry & OSAT capacity · AI chip market

Advanced nodes: TSMC extends its 2026 roadmap and scrambles to keep up with demand

TSMC's two 2nm (N2) fabs are fully booked. Supply chain sources report the company is now targeting 100,000 wafers per month on its N2 line by year-end 2026, up from near-zero at the start of the year when mass production launched. On 3nm, the original 150,000 WPM ceiling for the Taiwan plant has been revised to 180,000 WPM — 20% above earlier guidance — as demand from Nvidia, AMD, Apple, and Broadcom continues to outrun capacity.1
TSMC CEO C.C. Wei acknowledged on the company's most recent earnings call that supply shortages on leading-edge nodes will extend into 2027. That constraint is creating openings for rivals.
On the roadmap front, TSMC published an extended process timeline this month.2 The key milestones:
NodeNameTarget productionKey feature
2nmN22025 (ramping)First nanosheet FET; +10–15% speed vs. 3nm
2nm+N2P2026Performance/power extension of N2
1.6nmA162027 (delayed from 2026)Backside power delivery (Super Power Rail)
1.4nmA142028Second-gen nanosheet, no SPR
1.3nmA132029Direct shrink of A14; 97% optical scaling
The A16 slip from 2026 to 2027 is worth noting: Kevin Zhang confirmed TSMC will not use high-NA EUV for A16 or A14, relying instead on multi-pass low-NA EUV. That decision limits near-term litho-tool obsolescence risk but also caps achievable density gains.
Separately, Samsung SF2 (its 2nm-class node) is being positioned for a CPU order reportedly from AMD, though the deal remains unconfirmed.3 Intel Foundry, meanwhile, has suggested undisclosed design wins are in the pipeline, with its 18A node serving as a credibility benchmark.
The practical supply picture: TSMC controls the overwhelming majority of advanced-node capacity, and hyperscalers with multi-year purchase commitments — Apple, Nvidia, Broadcom — are locking out smaller developers.4 Engineers at midsize chip firms say getting a wafer reservation at 2nm is, for most companies, impossible today. The result is a growing bifurcation: a handful of mega-customers shape the leading edge, while everyone else optimizes chiplet architecture on older nodes.

Export controls: the H200 framework remains incoherent, and pressure mounts for allied alignment

The current U.S. approach to chip export controls in 2026 reads as a study in policy contradictions.
In December 2025, the Trump administration approved H200 exports to China. In January 2026, the Commerce Department formalized the regime — but with conditions that analysts describe as structurally incoherent:5
  • A 25% tariff on advanced AI chips meeting the performance threshold (effective January 14, 2026)
  • A per-case approval process replacing the prior blanket export ban
  • End-use certifications blocking military, intelligence, and WMD applications
  • An informal cap of roughly 1 million H200 units — approximately half the volume Chinese buyers had already ordered
The framework simultaneously acknowledges national security risk and opens an export channel. Nvidia has said it is uncertain whether any shipments will actually clear Chinese customs under the current rules.
A separate but related front: the Verified End User (VEU) exemption that allowed TSMC, Samsung, and SK Hynix to operate their China fabs without per-shipment U.S. equipment licenses expired on December 31, 2025. Since January 1, all three must obtain annual licenses from the Commerce Department to keep those fabs running. The mechanism gives Washington annual leverage over the operating terms of foreign-owned fabs in China.
The Institute for Security and Technology launched a dedicated AI Chip Export Control Initiative this month, focused on identifying compliance failure points and developing a multi-agency enforcement framework.6 Congressional pressure is also building: some lawmakers are pushing to replace entity-level controls with blanket country-level bans on semiconductor manufacturing equipment, while demanding that the U.S. use its leverage over American-origin components to force coordinated restrictions from the Netherlands and Japan.
The enforcement gap with allies remains significant. ASML's sales of advanced litho equipment to China roughly doubled between 2022 and 2024. U.S. threats of secondary sanctions have so far not produced binding multilateral alignment.
One signal worth tracking: China's semiconductor equipment imports rerouted through Singapore rose 17% year-over-year in 2025 to a record level, suggesting circumvention pathways are active and diversifying.

Foundry & OSAT capacity: CoWoS remains structurally undersupplied, Intel EMIB gains traction

The advanced packaging constraint that first surfaced in 2023 has not resolved — it has widened.
TSMC's CoWoS capacity has been structurally tight since 2023, with Nvidia alone holding over 50% of CoWoS allocation through 2027. Google was reportedly forced to cut its 2026 TPU production target from 4 million to 3 million units partly due to packaging supply limits.7 Morgan Stanley estimates TSMC's CoWoS capacity will grow from 120,000 wafers per month at end-2025 to 165,000 WPM by end-2026, and TSMC separately announced a $5 billion CoWoS expansion in Taiwan, targeting a 50% output increase by mid-2027.8
Intel's EMIB (Embedded Multi-Die Interconnect Bridge) is receiving renewed attention as a CoWoS alternative:9
  • Google's TPU v8e (targeting H2 2027) and Meta's custom CPU (targeting H2 2028) are both reportedly planning to use Intel EMIB
  • EMIB-T yield has reached approximately 90% according to analyst reports, vs. ~98% for TSMC CoWoS
  • EMIB's mask-scale advantage is substantial: EMIB-M currently achieves 6× reticle scaling, expanding to 8–12× by 2026–2027; CoWoS-S and CoWoS-L sit at roughly 3.3–3.5×
  • Intel is asking EMIB customers to commit to substrate prepayments, with four Taiwan and two Japan suppliers — including Ibiden and Unimicron — already locking in capacity
The substrate layer is tightening in parallel. ABF (Ajinomoto Build-up Film), the key interlayer material for advanced packaging substrates, is rising 30% in price from Q3 2026. Ibiden has approved an additional ¥280 billion investment in its Ono plant as part of a ¥500 billion capex program for FY2026–2028.
China's OSAT providers — long peripheral players — are trying to move into advanced packaging as CoWoS overflow creates opportunity. AI demand is straining global chip packaging supply broadly, and OSATs such as SPIL and Amkor are picking up spillover orders that TSMC can't serve.
ASE advanced packaging sample: a multi-chip module with central large die surrounded by eight smaller dies on a green substrate. Source: Digitimes
ASE advanced packaging sample: a multi-chip module with central large die surrounded by eight smaller dies on a green substrate. Source: Digitimes
Advanced packaging sample from ASE, illustrating the multi-die configurations now standard for AI accelerators. Source: Digitimes.

AI chip market: Broadcom and Marvell hold 80%+ of hyperscaler custom ASIC design, Nvidia projects $1T over Blackwell and Vera Rubin

The AI chip market in mid-2026 has a two-track structure: Nvidia's GPU franchise dominates open-market sales, while custom ASIC design is consolidating around a two-firm axis.
Broadcom and Marvell together account for over 80% of hyperscaler custom AI chip design partnerships.10 The split:
Design partnerMarket shareKey hyperscaler wins
Broadcom~70%Google TPU, OpenAI (pre-production), Meta MTIA, Anthropic, Apple (new, 2026)
Marvell20–25%AWS Trainium, Microsoft Maia
Neither firm sells branded data center chips. Both act as design-and-IP partners, with the hyperscaler absorbing all manufacturing and capex risk. Broadcom's gross margin runs at roughly 78.6% — above Nvidia's 73.5% — on a fraction of the capital intensity. Broadcom has locked in a Google supply agreement through 2031.
Marvell made a notable move in May 2026: it acquired Celestial AI for $3.25 billion, going deeper into photonic interconnect fabric to differentiate its chip-to-memory bandwidth story.
On the Nvidia side, the company estimated total Blackwell and Vera Rubin architecture chip sales at $1 trillion across 2026 and 2027 combined. That figure covers data center AI accelerator shipments at a scale no custom ASIC program approaches individually — though the aggregate of hyperscaler custom chips is growing rapidly.
The competitive dynamics to watch: hyperscalers are using dual-source strategies between Broadcom and Marvell (each project goes to one, not both), which structurally limits how deeply either firm can be displaced. The risk for both is customer in-house capability growth — Google in particular is building chip design muscle that could reduce its dependence on external design partners over time.
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Semiconductor Industry Weekly covers advanced node progress, export control policy, foundry and OSAT capacity, and the AI chip competitive landscape. Published weekly.

参考ソース

  1. 1TSMC scrambles to crank 2nm and 3nm output
  2. 2TSMC Releases New Roadmap, Rolls Out A13 Process
  3. 3Samsung vs. TSMC vs. Intel: Who's Winning the Foundry Market
  4. 4Foundry Capacity Is Limiting Who Competes At Leading Edge Nodes
  5. 5US China Chip Export Controls H200 2026: The Policy Shift Explained
  6. 6AI Chip Export Control Initiative – IST
  7. 7TSMC CoWoS capacity and demand dynamics
  8. 8Advanced Packaging Semiconductor Market 2026
  9. 9Intel Says EMIB Customers Back Substrate Prepayments
  10. 10Broadcom & Marvell: AI ASIC Design Partners

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